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White Electronic Designs
512KX32 SRAM / FLASH MODULE
FEATURES
Access Times of 25ns (SRAM) and 70, 90ns (FLASH) Packaging * 66 pin, PGA Type, 1.385" square HIP, Hermetic Ceramic HIP (Package 402) * 68 lead, Hermetic CQFP (G2T), 22.4mm (0.880") square (Package 509) 4.57mm (0.180") height. Designed to fit JEDEC 68 lead 0.990" CQFJ footprint (Figure 2). Package to be developed. 512Kx32 SRAM 512Kx32 5V Flash Organized as 512Kx32 of SRAM and 512Kx32 of Flash Memory with common Data Bus Low Power CMOS Commercial, Industrial and Military Temperature Ranges TTL Compatible Inputs and Outputs
WSF512K32-XXX
Built in Decoupling Caps and Multiple Ground Pins for Low Noise Operation Weight - 13 grams typical
FLASH MEMORY FEATURES
100,000 Erase/Program Cycles Sector Architecture * 8 equal size sectors of 64KBytes each * Any combination of sectors can be concurrently erased. Also supports full chip erase 5 Volt Programming; 5V 10% Supply Embedded Erase and Program Algorithms Hardware Write Protection Page Program Operation and Internal Program Control Time.
* This product is subject to change without notice. Note: Programming information available upon request.
Figure 1 - PIN CONFIGURATION FOR WSF512K32-29H2X Top View
1 I/O8 I/O9 I/O10 A14 A16 A11 A0 A18 I/O0 I/O1 I/O2 11 22 12 FWE2# SWE2# GND I/O11 A10 A9 A15 VCC FCS# SCS# I/O3 33 23 I/O15 I/O14 I/O13 I/O12 OE# A17 FWE1# I/O7 I/O6 I/O5 I/O4 I/O24 I/O25 I/O26 A7 A12 SWE1# A13 A8 I/O16 I/O17 I/O18 44 34 VCC SWE4# FWE4# I/O27 A4 A5 A6 FWE3# SWE3# GND I/O19 55 45 I/O31 I/O30 I/O29 I/O28 A1 A2 A3 I/O23 I/O22 I/O21 I/O20 66
OE# A0-18 SCS# FCS# FWE1# SWE1#
Pin Description
I/O0-31
56
Data Inputs/Outputs Address Inputs SRAM Write Enables SRAM Chip Select Output Enable Power Supply Ground Not Connected Flash Write Enables Flash Chip Select
A0-18 SWE1-4# SCS# OE# VCC GND NC FWE1-4# FCS#
Block Diagram
FWE2# SWE2# FWE3# SWE3# FWE4# SWE4#
512K x 8 Flash 512K x 8 SRAM
512K x 8 Flash 512K x 8 SRAM
512K x 8 Flash 512K x 8 SRAM
512K x 8 Flash 512K x 8 SRAM
I/O0-7
I/O8-15
I/O16-23
I/O24-31
May 2006 Rev. 9
1
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White Electronic Designs
WSF512K32-XXX
FIGURE 2 - PIN CONFIGURATION FOR WSF512K32-29G2TX
Top View
NC A0 A1 A2 A3 A4 A5 SWE3# GND SWE4# FWE1# A6 A7 A8 A9 A10 VCC
Pin Description
I/O0-31 A0-18 SWE1-4#
I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31
Data Inputs/Outputs Address Inputs SRAM Write Enables SRAM Chip Select Output Enable Power Supply Ground Not Connected Flash Write Enables Flash Chip Select
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
SCS# OE# VCC
0.940"
GND NC FWE1-4# FCS#
The WEDC 68 lead G2T CQFP fills the same fit and function as the JEDEC 68 lead CQFJ or 68 PLCC. But the G2T has the TCE and lead inspection advantage of the CQFP form.
A16 FCS#
OE# SWE2# A17 FWE2# FWE3# FWE4# A18
SCS# SWE1#
VCC
A11
A12
A13
A14
A15
Block Diagram
FWE1# SWE1# OE# A0-18 SCS# FCS# FWE2# SWE2# FWE3# SWE3# FWE4# SWE4#
512K x 8 Flash 512K x 8 SRAM
512K x 8 Flash 512K x 8 SRAM
512K x 8 Flash 512K x 8 SRAM
512K x 8 Flash 512K x 8 SRAM
I/O0-7
I/O8-15
I/O16-23
I/O24-31
May 2006 Rev. 9
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ABSOLUTE MAXIMUM RATINGS
Parameter Operating Temperature Storage Temperature Signal Voltage Relative to GND Junction Temperature Supply Voltage
Parameter Flash Data Retention 20 years
WSF512K32-XXX
SRAM TRUTH TABLE
Unit C C V C V SCS# H L L L OE# X L H X SWE# X H H L Mode Standby Read Read Write Data I/O High Z Data Out High Z Data In Power Standby Active Active Active
Symbol TA TSTG VG TJ VCC
Min -55 -65 -0.5 -0.5
Max +125 +150 7.0 150 7.0
NOTE: 1. FCS# must remain high when SCS# is low.
Flash Endurance (write/erase cycles)
100,000 Parameter OE# capacitance F/S WE1-4# capacitance F/S CS# capacitance D0-31 capacitance A0-18 capacitance
CAPACITANCE
Ta = +25C Symbol COE CWE CCS CI/O CAD Conditions Max Unit VIN = 0 V, f = 1.0 MHz 80 pF VIN = 0 V, f = 1.0 MHz 30 pF VIN = 0 V, f = 1.0 MHz 50 pF VI/O = 0 V, f = 1.0 MHz 30 pF VIN = 0 V, f = 1.0 MHz 80 pF
NOTE: 1. Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VIH VIL Min 4.5 2.2 -0.5 Max 5.5 VCC + 0.3 +0.8 Unit V V V
This parameter is guaranteed by design but not tested.
DC CHARACTERISTICS
VCC = 5.0V, VSS = 0V, -55C TA +125C Parameter Input Leakage Current Output Leakage Current SRAM Operating Supply Current x 32 Mode Standby Current SRAM Output Low Voltage SRAM Output High Voltage Flash VCC Active Current for Read (1) Flash VCC Active Current for Program or Erase (2) Flash Output Low Voltage Flash Output High Voltage Flash Output High Voltage Flash Low VCC Lock Out Voltage Symbol ILI ILO ICCx32 ISB VOL VOH ICC1 ICC2 VOL VOH1 VOH2 VLKO Conditions VCC = 5.5, VIN = GND to VCC SCS# = VIH, OE# = VIH, VOUT = GND to VCC SCS# = VIL, OE# = FCS# = VIH, f = 5MHz, VCC = 5.5 FCS# = SCS# = VIH, OE# = VIH, f = 5MHz, VCC = 5.5 IOL = 6mA, VCC = 4.5 IOH = -4.0mA, VCC = 4.5 FCS# = VIL, OE# = SCS# = VIH FCS# = VIL, OE# = SCS# = VIH IOL = 8.0mA, VCC = 4.5 IOH = -2.5 mA, VCC = 4.5 IOH = -100 A, VCC = 4.5 Min Max 10 10 550 90 0.4 250 300 0.45 0.85 x VCC VCC -0.4 3.2 Unit A A mA mA V V mA mA V V V V
2.4
4.2
NOTES: 1. The ICC current listed includes both the DC operating current and the frequency dependent component (@ 5 MHz). The frequency component typically is less than 2mA/MHz, with OE# at VIH. 2. ICC active while Embedded Algorithm (program or erase) is in progress. 3. DC test conditions: VIL = 0.3V, VIH = VCC - 0.3V
May 2006 Rev. 9
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SRAM AC CHARACTERISTICS
VCC = 5.0V, -55C TA +125C Parameter Read Cycle Read Cycle Time Address Access Time Output Hold from Address Change Chip Select Access Time Output Enable to Output Valid Chip Select to Output in Low Z Output Enable to Output in Low Z Chip Disable to Output in High Z Output Disable to Output in High Z Symbol tRC tAA tOH tACS tOE tCLZ1 tOLZ1 tCHZ1 tOHZ1 Min 25 0 25 15 3 0 12 12 -25 Max 25 ns ns ns ns ns ns ns ns ns Units Parameter Write Cycle Write Cycle Time Chip Select to End of Write Address Valid to End of Write Data Valid to End of Write Write Pulse Width Address Setup Time Address Hold Time Output Active from End of Write Write Enable to Output in High Z Data Hold from Write Time
WSF512K32-XXX
SRAM AC CHARACTERISTICS
VCC = 5.0V, -55C TA +125C Symbol Min tWC tCW tAW tDW tWP tAS tAH tOW1 tWHZ1 tDH 25 20 20 15 20 3 0 3 15 0 -25 Max ns ns ns ns ns ns ns ns ns ns Units
1. This parameter is guaranteed by design but not tested.
1. This parameter is guaranteed by design but not tested.
FIGURE 3 AC TEST CIRCUIT AC Test Conditions
I OL Current Source
D.U.T. C eff = 50 pf
VZ 1.5V (Bipolar Supply)
Parameter Input Pulse Levels Input Rise and Fall Input and Output Reference Level Output Timing Reference Level
Typ VIL = 0, VIH = 3.0 5 1.5 1.5
Unit V ns V V
I OH Current Source
Notes: VZ is programmable from -2V to +7V. IOL & IOH programmable from 0 to 16mA. Tester Impedance Z0 = 75 . VZ is typically the midpoint of VOH and VOL. IOL & IOH are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance.
May 2006 Rev. 9
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WSF512K32-XXX
FIGURE 4 - SRAM TIMING WAVEFORM - READ CYCLE
tRC
ADDRESS
tAA
tRC
ADDRESS
SCS#
tACS
tAA tOH
SOE#
tCHZ
tCLZ tOE tOLZ
DATA I/O
HIGH IMPEDANCE
DATA I/O
PREVIOUS DATA VALID
DATA VALID
tOHZ
DATA VALID
READ CYCLE 1, (SCS# = OE# = VIL, SWE# = FCS# = VIH)
READ CYCLE 2, (SWE# = FCS# = VIH)
FIGURE 5 - SRAM WRITE CYCLE - SWE# CONTROLLED
tWC
ADDRESS
tAW tCW
SCS#
tAH
tAS
SWE#
tWP tOW tWHZ tDW
DATA VALID
tDH
DATA I/O
WRITE CYCLE 1, SWE# CONTROLLED (FCS# = VIH)
FIGURE 6 - SRAM WRITE CYCLE - SCS# CONTROLLED
tWC
ADDRESS
tAS
SCS#
tAW tCW
tAH
tWP
SWE#
tDW
DATA I/O
DATA VALID
tDH
WRITE CYCLE 2, SCS# CONTROLLED (FCS# = VIH)
May 2006 Rev. 9 5 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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VCC = 5.0V, -55C TA +125C
Parameter Write Cycle Time Chip Select Setup Time Write Enable Pulse Width Address Setup Time Data Setup Time Data Hold Time Address Hold Time Write Enable Pulse Width High Duration of Byte Programming Operation (1) Chip and Sector Erase Time (2) Read Recovery Time Before Write VCC Set-up Time Chip Programming Time Output Enable Setup Time Output Enable Hold Time (4) Chip Erase Time (3) NOTES: 1. Typical value for tWHWH1 is 7ns. 2. Typical value for tWHWH2 is 1sec. 3. Typical value for Chip Erase Time is 8sec. 4. For Toggle and Data# Polling. tOES tOEH 0 10 64 tAVAV tELWL tWLWH tAVWL tDVWH tWHDX tWLAX tWHWL tWHWH1 tWHWH2 tGHWL tVCS 0 50 11 Symbol Min tWC tCS tWP tAS tDS tDH tAH tWPH 70 0 45 0 45 0 45 20 300 15 -70 Max
WSF512K32-XXX
FLASH AC CHARACTERISTICS - WRITE/ERASE/PROGRAM OPERATIONS, FWE# CONTROLLED
-90 Min 90 0 45 0 45 0 45 20 300 15 0 50 11 0 10 64 Max ns ns ns ns ns ns ns ns s sec s s sec ns ns sec Unit
FLASH AC CHARACTERISTICS - READ ONLY OPERATIONS
VCC = 5.0V, -55C TA +125C
Parameter Read Cycle Time Address Access Time Chip Select Access Time OE# to Output Valid Chip Select to Output High Z (1) OE# High to Output High Z (1) Output Hold from Address, FCS# or OE# Change, whichever is first 1. Guaranteed by design, not tested. tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX Symbol Min tRC tACC tCE tOE tDF tDF tOH 0 70 70 70 35 20 20 0 -70 Max Min 90 90 90 35 20 20 -90 Max ns ns ns ns ns ns ns Unit
May 2006 Rev. 9
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VCC = 5.0V, -55C TA +125C
WSF512K32-XXX
FLASH AC CHARACTERISTICS - WRITE/ERASE/PROGRAM OPERATIONS, FCS# CONTROLLED
Parameter
Write Cycle Time FWE# Setup Time FCS# Pulse Width Address Setup Time Data Setup Time Data Hold Time Address Hold Time FCS# Pulse Width High Duration of Programming Operation (1) Sector Erase Time (2) Read Recovery Time Chip Programming Time Chip Erase Time (3) NOTES: 1. Typical value for tWHWH1 is 7ns. 2. Typical value for tWHWH2 is 1sec. 3. Typical value for Chip Erase Time is 8sec. tAVAV tWLEL tELEH tAVEL tDVEH tEHDX tELAX tEHEL tWHWH1 tWHWH2 tGHEL
Symbol Min
tWC tWS tCP tAS tDS tDH tAH tCPH 70 0 45 0 45 0 45 20
-70 Max Min
90 0 45 0 45 0 45 20 300 15 0 11 64 0
-90 Max
Unit
ns ns ns ns ns ns ns ns 300 15 s sec ns sec sec
May 2006 Rev. 9
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WSF512K32-XXX
FIGURE 7 - AC WAVEFORMS FOR FLASH MEMORY READ OPERATIONS
tRC Addresses tACC FCS# tDF OE# tOE Addresses Stable
FWE#
tCE
tOH High Z
Outputs
High Z
Output Valid
NOTE: SCS# = VIH
May 2006 Rev. 9
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WSF512K32-XXX
FIGURE 8 - WRITE/ERASE/PROGRAM OPERATION, FLASH MEMORY FWE# CONTROLLED
Data# Polling Addresses 5555H tWC FCS# tGHWL OE# tWP FWE# tCS tWPH tDH Data tDS tOH A0H PD tOE tDF tWHWH1 tAS PA tAH PA tRC
D7#
DOUT
5.0 V tCE
NOTES: 1. PA is the address of the memory location to be programmed. 2. PD is the data to be programmed at byte address. 3. D7# is the output of the complement of the data written to the device.
4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence. 6. SCS# = VIH
May 2006 Rev. 9
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WSF512K32-XXX
FIGURE 9 - AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS FOR FLASH MEMORY
tAS Addresses 5555H
tAH 2AAAH 5555H 5555H 2AAAH SA
FCS# tGHWL OE# tWP FWE# tWPH tCS Data tDS tDH
AAH
55H
80H
AAH
55H
10H/30H
VCC tVCS
Notes: 1. SA is the sector address for Sector Erase. 2. SCS# = VIH
May 2006 Rev. 9
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WSF512K32-XXX
FIGURE 10 AC WAVEFORMS FOR DATA# POLLING DURING EMBEDDED ALGORITHM OPERATIONS FOR FLASH MEMORY
FCS#
tCH tDF tOE
OE# tOEH FWE#
tCE tOH D7 tWHWH 1 or 2 D0-D6 D0-D6 = Invalid tOE D7 tWHWH 1 or 2 D7 D7 Valid Data High Z D0-D7 Valid Data D7# D7 = Valid Data High Z
Note: SCS# = VIH
May 2006 Rev. 9
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WSF512K32-XXX
FIGURE 11 - WRITE/ERASE/PROGRAM OPERATION FOR FLASH MEMORY, CS# CONTROLLED
Data# Polling Addresses 5555H tWC FWE# tGHEL OE# tCP FCS# tWS tWHWH1 tAS PA tAH PA
tCPH tDH
Data tDS
A0H
PD
D7#
DOUT
5.0 V
NOTES: 1. PA represents the address of the memory location to be programmed. 2. PD represents the data to be programmed at byte address. 3. D7# is the output of the complement of the data written to the device.
4. DOUT is the output of the data written to the device. 5. Figure indicates the last two bus cycles of a four bus cycle sequence. 6. SCS# = VIH
May 2006 Rev. 9
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WSF512K32-XXX
PACKAGE 509: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2T)
25.15 (0.990) 0.26 (0.010) SQ 22.36 (0.880) 0.26 (0.010) SQ 4.57 (0.180) MAX 0.27 (0.011) 0.04 (0.002)
Pin 1
0.25 (0.010) REF
24.03 (0.946) 0.26 (0.010) 1 / 7 1.0 (0.040) 0.127 (0.005)
R 0.25 (0.010) 0.19 (0.007) 0.06 (0.002)
23.87 (0.940) REF
DETAIL A
1.27 (0.050) TYP 0.38 (0.015) 0.05 (0.002) 20.3 (0.800) REF SEE DETAIL "A"
The WEDC 68 lead G2T CQFP fills the same fit and function as the JEDEC 68 lead CQFJ or 68 PLCC. But the G2T has the TCE and lead inspection advantage of the CQFP form.
0.940"
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
May 2006 Rev. 9
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WSF512K32-XXX
PACKAGE 402: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H2)
35.2 (1.385) 0.38 (0.015) SQ
PIN 1 IDENTIFIER SQUARE PAD ON BOTTOM
25.4 (1.0) TYP
5.7 (0.223) MAX 3.81 (0.150) 0.1 (0.005) 2.54 (0.100) TYP 1.27 (0.050) 0.1 (0.005) 0.76 (0.030) 0.1 (0.005) 15.24 (0.600) TYP 1.27 (0.050) TYP DIA 0.46 (0.018) 0.05 (0.002) DIA 25.4 (1.0) TYP
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
ORDERING INFORMATION
W S F 512K32 - 29 X X X
LEAD FINISH: Blank = Gold plated leads A = Solder dip leads DEVICE GRADE: M = Military Screened I = Industrial C = Commercial
-55C to +125C -40C to +85C 0C to +70C
PACKAGE TYPE: H2 = Ceramic Hex In-line Package, HIP (Package 402) G2T = 22.4mm Ceramic Quad Flat Pack, CQFP (Package 509) ACCESS TIME (ns) 29 = 25ns SRAM and 90ns FLASH ORGANIZATION, 512K x 32 SRAM and Flash Flash SRAM WHITE ELECTRONIC DESIGNS CORP.
May 2006 Rev. 9
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